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| HM-6504/883 March 1997 4096 x 1 CMOS RAM Description The HM-6504/883 is a 4096 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses, data input and data output allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6504/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features * This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Low Power Standby . . . . . . . . . . . . . . . . . . . 125W Max * Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max * Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min * TTL Compatible Input/Output * Three-State Output * Standard JEDEC Pinout * Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max * 18 Pin Package for High Density * On-Chip Address Register * Gated Inputs - No Pull Up or Pull Down Resistors Required Ordering Information PACKAGE CERDIP TEMPERATURE RANGE -55oC to +125oC 200ns HM1-6504B/883 300ns HM1-6504/883 PKG. NO F18.3 Pinout HM-6504/883 (CERDIP) TOP VIEW A0 A1 A2 A3 A4 A5 Q W GND 1 2 3 4 5 6 7 8 9 18 VCC 17 A6 16 A7 15 A8 14 A9 13 A10 12 A11 11 D 10 E PIN A E W D Q DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 File Number 2993.1 6-134 HM-6504/883 Functional Diagram LSB A8 A7 A6 A0 A1 A2 A LATCHED ADDRESS REGISTER L 6 GATED ROW DECODER G 64 G D Q A GATED COLUMN DECODER AND DATA I/O D Q Q A 64 x 64 MATRIX 64 A 6 D D Q LATCH L LATCH L W LATCH L 6 A L Q LATCHED ADDRESS REGISTER 6 A E D L LATCH LSB A11 A5 A4 A3 A9 A10 NOTES: 1. All lines active high-positive logic. 2. Three-state Buffers: A high output active. 3. Control and Data Latches: L low Q = D and Q latches on rising edge of L. 4. Address Latches: Latch on falling edge of E. 5. Gated Decoders: Gate on rising edge of G. 6-135 HM-6504/883 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance JA JC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC +0.3V TABLE 1. HM-6504/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER Output Low Voltage SYMBOL VOL (NOTE 1) CONDITIONS VCC = 4.5V, IOL = 2mA VCC = 4.5V, IOH = -1.0mA VCC = 5.5V, VI = GND or VCC VCC = 5.5V, VO = GND or VCC VCC = 2.0V, E = VCC, IO = 0mA VCC = 5.5V, (Note 2), E = 1MHz, IO = 0mA VCC = 5.0V, E = VCC -0.3V, IO = 0mA GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC 1, 2, 3 -55oC TA +125oC 25 7 A mA MIN MAX 0.4 UNITS V Output High Voltage VOH 1, 2, 3 2.4 - V A A Input Leakage Current II 1, 2, 3 -1.0 +1.0 Output Leakage Current IOZ 1, 2, 3 -1.0 +1.0 Data Retention Supply Current ICCDR 1, 2, 3 Operating Supply Current ICCOP Standby Supply Current ICCSB 1, 2, 3 -55oC TA +125oC - 50 A NOTES: 1. All voltage referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP. 6-136 HM-6504/883 TABLE 2. HM-6504/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS (NOTES 1, 2) CONDITIONS VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V, Note 3 VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC HM-6504S/883 MIN 120 MAX 120 120 HM-6504B/883 MIN 200 MAX 200 220 - HM-6504/883 MIN 300 MAX 300 320 UNITS ns ns ns PARAMETER Chip Enable Access Time Address Access Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Address Hold Time Write Enable Pulse Width Write Enable Pulse Setup Time Early Write Pulse Setup Time Early Write Pulse Hold Time Data Setup Time Early Write Data Setup Time Data Hold Time Early Write Data Hold Time Read or Write Cycle Time SYMBOL (1) TELQV (2) TAVQV (5) TELEH (6) TEHEL 9, 10, 11 50 - 90 - 120 - ns (7) TAVEL (8) TELAX (9) TWLWH (10) TWLEH 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 0 40 20 70 - 20 50 60 150 - 20 50 80 200 - ns ns ns ns (11) TWLEL (13) TELWH (14) TDVWL (15) TDVEL (16) TWLDX (17) TELDX (18) TELEL 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 0 40 0 0 25 25 170 - 0 60 0 0 60 60 290 - 0 80 0 0 80 80 420 - ns ns ns ns ns ns ns NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL. 6-137 HM-6504/883 TABLE 3. HM-6504/883 ELECTRICAL PERFORMANCE SPECIFICATIONS HM-6504S/883 LIMITS PARAMETER Input Capacitance SYMBOL CI CONDITIONS VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground VCC = 4.5 and 5.5V NOTE 1 TEMPERATURE TA = +25oC MIN - MAX 8 UNITS pF Output Capacitance CO 1 TA = +25oC - 10 pF Chip Enable Output Disable Time Chip Enable Output Disable Time (3) TELQX 1 -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC 5 - ns (4) TEHQZ VCC = 4.5 and 5.5V HM-6504S/883 VCC = 4.5 and 5.5V HM-6504B/883 VCC = 4.5 and 5.5V HM-6504/883 1 - 50 ns 1 - 80 ns 1 - 100 ns Write Enable Read Mode Setup Time (12) TWHEL VCC = 4.5 and 5.5V 1 0 - ns High Level Output Voltage NOTE: VOHL VCC = 4.5V, IO = -100A 1 -55oC TA +125oC VCC 0.4 - V 1. The parameters listed in Table 3 are controlled via design, or process parameters are characterized upon initial design and after major process and/or design changes. f TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 6-138 HM-6504/883 Timing Waveforms (7) TAVEL A (6) TEHEL E (1) TELQV (3) TELQX (8) TELAX (7) TAVEL NEXT ADD TELEH (5) TELEL (18) TEHEL (6) ADD VALID (4) TEHQZ VALID DATA OUTPUT HIGH Z Q HIGH W TIME REFERENCE -1 0 HIGH Z 1 2 3 4 5 FIGURE 1. READ CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L E H W X H H H H X H A X V X X X X V OUTPUT Q Z Z X V V Z Z Memory Disabled Cycle Begins, Addresses are Latched Output Enabled Output Valid Read Accomplished Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION The address information is latched in the on-chip registers on the falling edge of E (T = 0). Minimum address set up and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1) the output becomes enabled but the data is not valid until during time (T = 2). W must remain high for the read cycle. After the output data has been read, E may return high (T = 3). This will disable the output buffer and all input, and ready the RAM for the next memory cycle (T = 4). 6-139 HM-6504/883 Timing Waveforms (Continued) (7) TAVEL A (6) TEHEL E (11) (13) TWLEL TELWH W (15) TDVEL D HIGH-Z Q TIME REFERENCE -1 0 1 2 3 4 (17) TELDX (15) TDVEL NEXT DATA HIGH-Z (11) TWLEL (8) TELAX (7) TAVEL NEXT ADD (18) TELEL (5) TELEH ADD VALID (6) TEHEL DATA VALID FIGURE 2. EARLY WRITE CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 H L E H W X L X X X L A X V X X X V D X V X X X V OUTPUT Q Z Z Z Z Z Z Memory Disabled Cycle Begins, Addresses are Latched Write in Progress Internally Write Completed Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION The early write cycle is the only cycle where the output is guaranteed not to become active. On the falling edge of E (T = 0), the addresses, the write signal, and the data input are latched in on-chip registers. The logic value of W at the time E falls determines the state of the output buffer for that cycle. Since W is low when E falls, the output buffer is latched into the high impedance state and will remain in that state until E returns high (T = 2). For this cycle, the data input is latched by E going low; therefore, data set up and hold times should be referenced to E. When E (T = 2) returns to the high state, the output buffer and all inputs are disabled and all signals are unlatched. The device is now ready for the next cycle. 6-140 HM-6504/883 Timing Waveforms (Continued) (7) TAVEL (8) TELAX (7) TAVEL NEXT ADD (18) TELEL (5) TELEH E (6) TEHEL (9) TWLWH W (14) TDVWL D (3) TELQX Q HIGH Z DATA VALID (4) TEHQZ HIGH Z (16) TWLDX (10) TWLEH (6) TEHEL A ADD VALID TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 3. LATE WRITE CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L H H X H E H W X H A X V X X X X V D X X V X X X X OUTPUTS Q Z Z X X X Z Z Memory Disabled Cycle Begins, Addresses are Latched Write Begins, Data is Latched Write In Progress Internally Write Completed Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION The late write cycle is a cross between the early write cycle and the read-modify-write cycle. Recall that in the early write, the output is guaranteed to remain high impedance, and in the read-modify-write, the output is guaranteed valid at access time. The late write is between these two cases. With this cycle the output may become active, and may become valid data, or may remain active but undefined. Valid data is written into the RAM if data setup, data hold, write setup and write pulse widths are observed. 6-141 HM-6504/883 Test Load Circuit DUT (NOTE 1) CL IOH + - 1.5V IOL EQUIVALENT CIRCUIT NOTE: 1. Test head capacitance includes stray and jig capacitance. Burn-In Circuit HM-6504/883 CERDIP VCC F3 F4 F5 F6 F7 F8 F2 F1 1 2 3 4 5 6 7 8 9 A0 A1 A2 A3 A4 A5 Q W GND VCC 18 A6 17 A7 16 A8 15 A9 14 A10 13 A11 12 D 11 E 10 F9 F10 F11 F12 F13 F14 F2 F0 C1 NOTES: All resistors 47k 5%. F0 = 100kHz 10%. F1 = F0 / 2, F2 = F1 / 2, F3 = F2 / 2 . . . F12 = F11 / 2. VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. C1 = 0.01F Min. 6-142 HM-6504/883 Die Characteristics DIE DIMENSIONS: 136 x 169 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.79 x 105 A/cm2 LEAD TEMPERATURE (10s soldering): 300oC Metallization Mask Layout HM-6504/883 A1 A2 A3 A0 VCC A6 A7 A8 A4 A5 A9 A10 A11 Q W GND E D NOTE: 1. Pin numbers correspond to DIP Package only. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6-143 |
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